Amazon Leo is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity to unserved and underserved communities around the world.
As a Senior Digital ATE Test Engineer, you will be a key contributor to the development and execution of high-volume production test solutions for custom modem and communication SoCs powering Amazon Leo's satellite constellation. You will partner closely with DFT, ASIC design, and manufacturing teams to translate design-for-test content into production-ready test programs from initial pattern conversion and silicon bring-up through high-volume manufacturing release.
This role demands deep expertise in digital ATE test methodology for complex modem/communication processors, with a strong emphasis on pattern conversion workflows (STIL/WGL to ATE-native formats), production test program bring-up, high-speed I/O and SERDES characterization and production testing, and tight collaboration with DFT teams to ensure comprehensive fault coverage and test quality. You must be responsive, flexible, and able to succeed within an open, collaborative, cross-functional environment.
Export Control Requirement:
Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.
Key job responsibilities
- Develop and own production test programs for complex digital/modem SoCs on Teradyne UltraFLEX and Advantest platforms, from initial bring-up through high-volume manufacturing release.
- Lead pattern conversion efforts: translate DFT-generated patterns (STIL/WGL) into tester-executable formats (ATP/PAT), validating coverage and ensuring functional equivalence.
- Partner directly with DFT teams to define test insertion strategy, review pattern quality, resolve coverage gaps, and optimize scan/MBIST/BIST content for ATE execution.
- Develop and execute high-speed I/O and SERDES characterization and production test methodologies, including eye diagram analysis, jitter measurement, BER testing, and TX/RX equalization optimization at 30+ Gbps data rates.
- Run and optimize test vectors on ATE platforms, tuning timing, levels, and equalization parameters to ensure repeatability and yield across process corners, voltage and temperature.
- Define SERDES test limits and guardbands based on characterization data, ensuring production screening captures marginal devices while maintaining yield targets.
- Develop and execute test strategies for on-chip one-time programmable (OTP) memory, including understanding of programming mechanisms, verification methodologies, and common challenges such as bit yield optimization, programming voltage margins, redundancy schemes, and post-programming reliability validation
- Review and provide feedback on load board, socket, and probe card designs—assessing signal integrity, power integrity, and layout best practices for high-speed I/O interfaces.
- Define test limits and guardbands based on characterization data, ensuring production screening captures marginal devices while maintaining yield targets and proactively identify test readiness risks, coverage gaps, and optimization opportunities.
- Support qualification activities including burn-in board design, HTOL, ESD, and reliability testing.
- Conduct failure analysis, drive root-cause resolution, and close test correlation issues across the supply and manufacturing chain.
